Single-Event Transient Effect on a Self-Biased Ring-Oscillator PLL and an LC PLL Fabricated in SOS Technology

The single-event transient effect on a ring-oscillator based and an LC-tank based phased-locked loop circuits fabricated in a 0.25 μm silicon-on-sapphire technology is analyzed with circuit-level simulations followed by laser experiments. Advantages of the LC-tank based circuits in terms of single-event tolerance over the ring-oscillator based circuits are discussed.

[1]  Yann Deval,et al.  Investigation of single-event transients in voltage-controlled oscillators , 2003 .

[2]  T. D. Loveless,et al.  A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS , 2007, IEEE Transactions on Nuclear Science.

[3]  Francis J. Kub,et al.  Radiation hardened SOS MOSFET technology for infrared focal plane readouts , 1990 .

[4]  Tao Wang,et al.  A RHBD LC-Tank Oscillator Design Tolerant to Single-Event Transients , 2010, IEEE Transactions on Nuclear Science.

[5]  E. Xiao,et al.  A 2.5 GHz radiation hard fully self-biased PLL using 0.25 µm SOS-CMOS technology , 2009, 2009 IEEE International Conference on IC Design and Technology.

[6]  T. D. Loveless,et al.  Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators , 2007, IEEE Transactions on Nuclear Science.

[7]  T. D. Loveless,et al.  A Hardened-by-Design Technique for RF Digital Phase-Locked Loops , 2006, IEEE Transactions on Nuclear Science.

[8]  Tao Wang,et al.  Single-Event Transients Effects on Dynamic Comparators in a 90 nm CMOS Triple-Well and Dual-Well Technology , 2009, IEEE Transactions on Nuclear Science.

[9]  O. Musseau Single-event effects in SOI technologies and devices , 1996 .

[10]  M. Horowitz,et al.  Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  C. Poivey,et al.  Pulsed-laser testing methodology for single event transients in linear devices , 2004, IEEE Transactions on Nuclear Science.

[12]  H. Saito,et al.  Radiation-hardened phase-locked loop fabricated in 200 nm SOI-CMOS , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[13]  L. Massengill,et al.  Towards SET Mitigation in RF Digital PLLs: From Error Characterization to Radiation Hardening Considerations , 2005, IEEE Transactions on Nuclear Science.

[14]  Shi-Jie Wen,et al.  Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter , 2012, J. Electron. Test..