Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes
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[1] Xuhua Yang,et al. BM-RCGL: Benchmarking Approach for Localization of Reliability-Critical Gates in Combinational Logic Blocks , 2022, IEEE Transactions on Computers.
[2] Qianwei Zhou,et al. Uniform non-Bernoulli sequences oriented locating method for reliability-critical gates , 2021 .
[3] Peng Liu,et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults , 2020, Journal of Electronic Testing.
[4] Behnam Ghavami,et al. Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] C. Kim,et al. Understanding the Key Parameter Dependences Influencing the Soft-Error Susceptibility of Standard Combinational Logic , 2020, IEEE Transactions on Nuclear Science.
[6] Jin Sun,et al. Resource Management for Improving Soft-Error and Lifetime Reliability of Real-Time MPSoCs , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Jianhui Jiang,et al. A Locating Method for Reliability-Critical Gates with a Parallel-Structured Genetic Algorithm , 2019, Journal of Computer Science and Technology.
[8] Tommy W. S. Chow,et al. Fault diagnosis on wireless sensor network using the neighborhood kernel density estimation , 2019, Neural Computing and Applications.
[9] Walid Ibrahim,et al. Multithreaded and Reconvergent Aware Algorithms for Accurate Digital Circuits Reliability Estimation , 2019, IEEE Transactions on Reliability.
[10] Jungang Lou,et al. A Fast and Effective Sensitivity Calculation Method for Circuit Input Vectors , 2019, IEEE Transactions on Reliability.
[11] Kin P. Cheung,et al. Reliability of Nanoelectronic Devices , 2017 .
[12] Miroslav Kvassay,et al. Reliability Analysis of Multiple-Outputs Logic Circuits Based on Structure Function Approach , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Walid Ibrahim,et al. Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates , 2016, IEEE Transactions on Computers.
[14] Walid Ibrahim,et al. Accurate and Efficient Estimation of Logic Circuits Reliability Bounds , 2015, IEEE Transactions on Computers.
[15] M. Shearer,et al. Partial Differential Equations: An Introduction to Theory and Applications , 2015 .
[16] Hao Chen,et al. A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation , 2014, IEEE Transactions on Computers.
[17] John P. Hayes,et al. Design, Analysis and Test of Logic Circuits Under Uncertainty , 2012, Lecture Notes in Electrical Engineering.
[18] Hao Chen,et al. Reliability evaluation of logic circuits using probabilistic gate models , 2011, Microelectron. Reliab..
[19] Kartik Mohanram,et al. Reliability Analysis of Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] Premachandran R. Menon,et al. Critical Path Tracing - An Alternative to Fault Simulation , 1983, 20th Design Automation Conference Proceedings.
[21] Hans Janssen,et al. Monte-Carlo based uncertainty analysis: Sampling efficiency and sampling convergence , 2013, Reliab. Eng. Syst. Saf..
[22] Sanjukta Bhanja,et al. Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.