Extraction of defect size distributions in an IC layer using test structure data

This paper demonstrates the need for specialized test structures and algorithms to obtain defect characteristics which are necessary for accurate yield prediction. Using one such specialized test structure, a general methodology for extracting size distribution parameters for both shorts and opens in any IC layer, which is independent of defect and yield models, is developed in this paper. The application of this methodology is illustrated by means of a fabrication experiment. >

[1]  Jochen A. G. Jess,et al.  Qualification and quantification of process-induced product-related defects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[2]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[3]  A. Ferris-Prabhu.  Role of defect size distribution in yield modeling , 1985, IEEE Transactions on Electron Devices.

[4]  C. H. Stapper.  The defect-sensitivity effect of memory chips , 1986 .

[5]  C. Stapper.  Yield statistics for large area ICs , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[7]  Charles H. Stapper,et al.  Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..

[8]  R. M. Warner.  Applying a composite model to the IC yield problem , 1974 .

[9]  Edward R. Dougherty,et al.  Probability and Statistics for the Engineering, Computing and Physical Sciences , 1990 .

[10]  J. Meindl,et al.  A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy , 1990 .

[11]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  A. V. Ferris-Prabhu,et al.  Modeling the critical area in yield forecasts , 1985 .

[13]  C. Stapper.  The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .

[14]  Wojciech Maly,et al.  Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.

[15]  Michael A. Saunders,et al.  User''s guide for NPSOL (Ver-sion 4.0): A FORTRAN package for nonlinear programming , 1984 .