Analysis of bit cost and performance for stacked type chain PRAM

The analysis of bit cost and the performance of stacked type chain PRAM bas been newly described. Using the optimized number of layer the bit cost of stacked type chain PRAM with stacked horizontal plane structure or BiCS type structure can be reduced compared with that of 1 layer NAND flash memory. The smallest bit cost of BiCS type structure is as small as 0.08 of 1 layer NAND flash memory using the optimized number of layer of 64. The delay time of WL and BL of stacked type chain PRAM with BiCS type structure has been estimated. Using the optimized number layer of 64 for realizing smallest bit cost the delay time of WL and BL are less than 5ns which is competitive to DRAM. Because of estimated high speed characteristics and low bit cost, the chain PRAM wth BiCS type structure is the promising candidate for replacing DRAM and NAND flash memory.

[1]  Sho Kato,et al.  Design Technology of Stacked‐Type Chain PRAM , 2011, SDM 2011.

[2]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[3]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[4]  Y. Sasago,et al.  Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming gigabyte-per-second throughput , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[5]  Kunishima,et al.  High-density chain ferroelectric random-access memory (CFRAM) , 1997, Symposium 1997 on VLSI Circuits.

[6]  Shigeyoshi Watanabe,et al.  Design method of stacked type MRAM with NAND structured cell , 2013 .

[7]  Fumio Horiguchi,et al.  A 33-ns 64-Mb DRAM , 1991 .

[8]  T. Kobayashi,et al.  Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[9]  Shigeyoshi Watanabe,et al.  Design Method for Stacked FeRAM with Oxide-Channel Transistor , 2011 .

[10]  Byung-Gil Choi,et al.  A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation , 2007, IEEE Journal of Solid-State Circuits.

[11]  Minemura Hiroyuki,et al.  Phase-change memoy driven by poly-Si transistor enabling three-dimensional stacking , 2011 .

[12]  Kinam Kim,et al.  A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM) , 2005, IEEE Journal of Solid-State Circuits.