A 9.6 Gb/s HEMT ATM switch LSI for B-ISDN

An asynchronous transfer mode (ATM) switch LSI has been designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility transistor (HEMT) technology. To enhance the high-speed performance of direct coupled FET logic (DCFL), event control logic was used for the first-in first-out (FIFO) buffer circuit, instead of conventional static memory. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operation frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s.<<ETX>>

[1]  Y. Asada,et al.  A gigahertz cryogenic HEMT pseudorandom number generator chip set , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[2]  Yasuro Shobatake,et al.  A 400Mb/s 8x8 BICMOS ATM Switch LSI With 1280 On-chip Shared Memory , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  M. Suzuki,et al.  A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates , 1991 .

[4]  Koso Murakami,et al.  A development of a high speed ATM switching LSIC , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[5]  F. Van Simaeys,et al.  A 600Mb/s 16x16 Switching Element Chipset For Broadband ISDN , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  E. Mitani,et al.  A 1.2-ns HEMT 64-kb SRAM , 1991 .

[7]  M. Abe,et al.  A Hemt Lsi For A Multibit Data Register , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[8]  H. Matsuno,et al.  A Scheduling Content-addressable Memory For ATM Space-division Switch Control , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.