Maximum Power-up Current Estimation Based on Genetic Algorithm

When scaling down into deep sub micron of VLSI design, the static power becomes a bottleneck of low power design. Power gating is a powerful and applicable solution to reduce both dynamic power and static power. Maximum current is a significant parameter for power gated circuit designs, which is determined by the maximum of all possible power up and normal switching current. How to estimate the maximum current of a power gated circuit quickly and accurately is a new problem. Hazards are found to consume a significant part of total power during runtime. In this paper, we develop an experiment and observe that hazards exit during powering up as well as normal runtime and dissipate a great deal of energy. A new genetic algorithm based method is proposed to estimate the maximum power up current for combinational circuits considering hazard power. Experiments with the ISCAS85 benchmark circuits show power gated circuits may consume larger maximum current in powering up phase than normal runtime phase and our algorithm can obtain 12.90% improvement of maximum power up current within only 2.77% time than random simulation due to its lower time complexity.