A 3.1–6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation

This paper presents a design of 3.1–6.0 GHz power amplifier (PA) 0.18 µm CMOS technology for ultra-wideband (UWB) applications. The UWB PA employs two stages amplifier and inter-stage circuit to provide a wider gain and gain flatness while shunt resistive feedback technique is adopted at the input stage to provide wideband input matching. To obtain high and flat gain, good group delay variation and linearity at the same time, the inductive peaking technique and Class A PA are employed at the first stage and the second stage. The measurement results indicated that the proposed PA design has an average gain of 10±1 dB, an input return loss (S11) less than −6 dB, an output return loss (S22) less than −7 dB, and group delay variation of ±195.5 ps are obtained across the whole band. A good input 1dB compression point of −5 dBm and input third-order intercept point of 5 dBm at 5 GHz are achieved while consuming 30 mW power from 1.8 V supply voltage.