Low Power Design by Determinstic Test Vectors Generation

In the process of testing combinational circuit using BIST method,a determinstic test vectors with low power consumption generation structure is presented,which decreases the test power consumption in the circumstances of ensuring the higher stuck-at fault coverage. The proposed method uses a structure of configurable LFSR to generate the deterministic test vectors and combines the theory of single switching activities logic with operating in different clock to achieve the single switching vectors between each determinstic vectors. According to experimenting in ISCAS'85,the proposed scheme verifies not only to improve the fault coverage but also shorten the test time and effectively reduce the total power consumption,average power consumption and peak power consumption in CUT.