A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders

A sign select Booth encoder reduces transistor count of multipliers. This encoder is applied in a 54/spl times/54 b multiplier in 0.25 /spl mu/m CMOS technology. Because of the rapid progress in VLSI design technologies, consecutive improvements in operational speed and design integration are made. As a result of these improvements, interactive real-time 3D graphics applications have become available even in personal computers.

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