Optimized reseeding by seed ordering and encoding

Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of seeds determines the required storage either on the ATE or the chip being tested. These techniques interleave pseudorandom and deterministic cycles rather than first applying all of the pseudorandom cycles and then the deterministic cycles. The decision of when to change from a pseudorandom cycle to a deterministic cycle is made by comparing the final state of the pseudorandom cycle with previously generated ATPG patterns or by carrying out fault simulation on the final state. Which deterministic pattern is chosen for the deterministic cycle critically influences the remainder of the test. A methodology for doing this is described. In addition to interleaving test cycles, it is possible to use partial cycles in which the PRPG operates for a few clocks without loading the scan chains. This allows a new seed to be present without loading the seed from the ATE or controller. As might be suspected, this reduces the number of stored seeds at the penalty of more complexity in the control sequence. These techniques were simulated and compared with conventional reseeding for some ISCAS'89 benchmarks. Improvements varied between 25% and 85% in the required seed storage.

[1]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  Nur A. Touba,et al.  Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[3]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[4]  Hans-Joachim Wunderlich,et al.  Multiple distributions for biased random test patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[5]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[6]  C. Landrault,et al.  On calculating efficient LFSR seeds for built-in self test , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[7]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[8]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[9]  Eric Lindbloom,et al.  Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test , 1983, IBM J. Res. Dev..

[10]  Erik H. Volkerink,et al.  Efficient seed utilization for reseeding based compression [logic testing] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[11]  Ahmad A. Al-Yamani,et al.  BIST reseeding with very few seeds , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[12]  Nur A. Touba,et al.  Test point insertion based on path tracing , 1996, Proceedings of 14th VLSI Test Symposium.

[13]  Subhasish Mitra,et al.  Efficient Seed Utilization for Reseeding based Compression , 2003 .

[14]  Nur A. Touba,et al.  Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[15]  Janusz Rajski,et al.  Test Data Decompression for Multiple Scan Designs with Boundary Scan , 1998, IEEE Trans. Computers.

[16]  Melvin A. Breuer,et al.  Test embedding with discrete logarithms , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Ahmad A. Al-Yamani,et al.  Seed encoding with LFSRs and cellular automata , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  Hans-Joachim Wunderlich,et al.  Pattern generation for a deterministic BIST scheme , 1995, ICCAD.

[19]  Ahmad A. Al-Yamani,et al.  Built-in reseeding for serial BIST , 2003, Proceedings. 21st VLSI Test Symposium, 2003..