Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits

Quasi adiabatic circuits like the efficient charge recovery logic (ECRL) are known to reduce dynamic power dissipation of digital CMOS circuits significantly. The possible operation frequencies have been continuously increased due to technology scaling. Anyway, the field of operation is limited to medium performance applications. If it was possible to operate a given adiabatic circuit also at extremely high frequencies there would be many new applications: A circuit working at a medium frequency most of the time and at high frequencies only for some burst mode operations could be implemented in adiabatic logic. This paper presents a new perspective of adiabatic circuits called adiabatic mode circuits. These circuits can be operated in a quasi adiabatic low-power mode but also in a high frequency domino mode if high speed data processing is required. Based on the 3-transistor DRAM cell a novel 3-transistor memory cell capable for adiabatic and conventional operation is presented. Thus new systems with a small total power consumption but temporarily high performance can be constructed.