A low-cost dual-mode deinterleaver design

In this paper, an efficient design of dual mode deinterleaver for both IEEE 802.16 and digital video broadcasting (DVB) standards is presented. The paper first proposes a systematic data allocation method for the design of matrix transposer which can be used to realize the block deinterleaver adopted by IEEE 802.16 based on the multi- bank memory architecture. In addition, multiple input/output data can be grouped together in order to further reduce the memory access frequency such that the required number of banks and ports for the memory can be both reduced. Similarly, the multi-bank memory design approach can also be applied for the byte-level convolutional deinterleaver adopted in DVB system by realizing the multiple delay branches as the circular buffer. Finally, these two different deinterleaving standards can be further integrated into a single design suitable for those dual-mode communication systems. Our implementation results show that the dual mode deinterleaver can run up to 150 Mhz, and consume about 38.5k gates. The same design methodology can also be applied for the design of interleavers .

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