High speed CMOS POS PLA using predischarged OR array and charge sharing AND array

A family of four PLAs using triggered decoders charge sharing is presented. They can be classified into two types. In the front of the OR-AND array, the two types 1 and 2 use 1-b or 2-b triggered decoders, respectively. Type 1 is a single-phase dynamic CMOS POS (NOT-NOT)-(NOT-NOR)-(NOT-NOT) PLAs in a product of sums (POS) using CMOS domino logic in the OR array and charge sharing logic in the AND array. Type 2 is a single-phase dynamic CMOS POS OR-(NOT-NOR)-(NOT-NOT) PLA in a POS using predischarged OR gates like NMOS domino logic and charge sharing logic. By using charge sharing for the implementation of a cascaded AND array in types 1 and 2, and by using a triggered input technique to replace ground switches, faster PLAs that require lower power dissipation than the conventional fastest CMOS SOP (NOT-NOR)-(NOT-NOT)-(NOR-NOT) PLA in a sum of products (SOP) are achieved. By using triggered 2-b decoders on the input during the precharge time, the capacitance of an input minterm of a PLA can be minimized to reduce power consumption. >