A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient

A novel convolution computing paradigm based on the NOR Flash Array is proposed. Significant improvements both in computing speed and energy consumption are achieved compared to CMOS-based logic computing paradigms. Regarding to the feature extraction task from a 256×256 image, the computing speed of 3.9×104 frame per second (fps) and the energy consumption of 0.057nJ/pixel are achieved using the proposed computing paradigm.

[1]  Shimeng Yu,et al.  Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems. , 2014, ACS nano.

[2]  Piotr Dudek,et al.  A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Peng Huang,et al.  Optimized learning scheme for grayscale image recognition in a RRAM based analog neuromorphic system , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[4]  Wancheng Zhang,et al.  A Programmable Vision Chip Based on Multiple Levels of Parallel Processors , 2011, IEEE Journal of Solid-State Circuits.

[5]  อนิรุธ สืบสิงห์,et al.  Data Mining Practical Machine Learning Tools and Techniques , 2014 .

[6]  Peng Huang,et al.  Compact Model of HfOX-Based Electronic Synaptic Devices for Neuromorphic Computing , 2017, IEEE Transactions on Electron Devices.

[7]  John G. Proakis,et al.  Digital signal processing (3rd ed.): principles, algorithms, and applications , 1996 .

[8]  Bin Zhang,et al.  Hardware Implementation of Reconfigurable 1D Convolution , 2016, J. Signal Process. Syst..

[9]  Piotr Dudek,et al.  A general-purpose processor-per-pixel analog SIMD vision chip , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Bernabé Linares-Barranco,et al.  An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors , 2012, IEEE Journal of Solid-State Circuits.

[11]  Yang Song,et al.  HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis , 2009, IEEE Journal of Solid-State Circuits.

[12]  Hideto Hidaka,et al.  40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{\circ}$C , 2014, IEEE Journal of Solid-State Circuits.

[13]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[14]  Pritish Narayanan,et al.  Neuromorphic devices and architectures for next-generation cognitive computing , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).