论文信息 - An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold

An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold

A recycling two-step architecture with a very low input current comparator is presented to implement an 8-b analog-to-digital converter (ADC) with an integrating sample and hold circuit that yields a 22-Msps conversion rate with a 10-MHz input. This two-step recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on two-metal, f/sub T/=8.5 GHz, npn bipolar junction transistor (BJT) application-specific integrated circuits.<<ETX>>

S. G. Burns | S. Wongkittikriwon

[1] Takeshi Yamaguchi,et al. A dual 4-bit, 1.5 Gs/s analog to digital converter , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[2] J. Doernberg,et al. A 10-bit 5-Msample/s CMOS two-step flash ADC , 1989 .

[3] Jens Horstmann,et al. Metastability behavior of CMOS ASIC flip-flops in theory and test , 1989 .

[4] M. F. Tompsett,et al. A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[5] M. K. Mayes,et al. A multistep A/D converter family with efficient architecture , 1989 .

[6] Masao Hotta,et al. A 10-bit 20-MHz two-step parallel A/D converter with internal S/H , 1989 .

[7] D. Seitzer,et al. A 1.9 Gbit/s monolithic comparator implemented on an analog bipolar array , 1990, Proceedings on Bipolar Circuits and Technology Meeting.

[8] R. Petschacher,et al. A 10-b 75-MSPS subranging A/D converter with integrated sample and hold , 1990 .