Design and performance of the 5 GHz waveform digitizing chip DRS3

The DRS3 chip is a radiation hard switched capacitor array (SCA) fabricated in a 0.25 mum CMOS process. It features 12 channels with 1024 bins each at a sampling rate of up to 5 GHz. Its signal-to-noise ratio is equivalent to 11.5 bits and the integral nonlinearity is 0.5 per mille with a temperature coefficient below 50 ppm per degree C. A special readout mode can be used to digitize only a certain region of interest from the waveform, bringing down the readout time to 3 mus for a signal which is hundred samples wide. The high channel density and superior electrical characteristics allow for new experiments with excellent pile-up rejection and pulse shape discrimination, while simultaneously eliminating the need for conventional ADCs and TDCs.