Hardware Support for Arithmetic Units of Processor with Multimedia Extension

Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (single instruction multiple data) IEEE FPU (floating-point unit). To verify the correctness and effectiveness of these methods, a multimedia coprocessor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good tradeoff between cost and performance.

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