Analyses of two run march tests with address decimation for BIST procedure

Conventional memory tests based on only one run have constant and low faults coverage especially for Pattern Sensitive Faults (PSF). To increase faults coverage the multiple run March test algorithms have been used. In a case of multiple memory test execution the consecutive memory address sequences and their relations or optimal set of backgrounds are very important to achieve high fault coverage. In the paper we will focus on short, effective and with low hardware overhead memory test procedures suitable especially for BIST systems. Therefore we will analyze two run march tests with address decimation with index q=2, which seems to be easiest to implement as multiple run march test.

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