Asynchronous transfer mode cell delineator implementations

Several algorithms for performing cell delineation on a bit-serial and octet-parallel basis are considered. Four algorithms were implemented in total, two bit-serial and two octet-parallel, for the design of cell delineators through to netlist generation. Analysis is provided for post-synthesis designs detailing speed, area and power parameters for each implementation at an input data rate of 160 Mbps and 1280 Mbps.

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