Tradeoffs in processor/memory interfaces for superscalar processors

The current scheme of dealing with data cache misses is not well-suited for superscalar processors. In this scheme, the processor is blocked by holding its clock low until the missing cache block can be fetched from memory and inserted into the cache. From the processor's viewpoint, the miss did not occur. From the user's viewpoint, the execution time was lengthened in direct proportion to the number of cache misses. This scheme has the potential of reducing the parallelism of superscalar processors with high issue rate to sub-unity values. The above scheme can be termed blocking. Two less-restrictive schemes are possible for interfacing processors to the rst level of the data memory system: