Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X.

[1]  Enrico Macii,et al.  NBTI-aware power gating for concurrent leakage and aging optimization , 2009, ISLPED.

[2]  Yu Cao,et al.  The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Kaushik Roy,et al.  Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI , 2006, 2006 International Conference on Computer Design.

[4]  Ku He,et al.  Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Yu-Guang Chen,et al.  NBTI-aware power gating design , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[6]  Lei He,et al.  Distributed sleep transistor network for power reduction , 2003, DAC '03.

[7]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[8]  James H. Stathis,et al.  The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..

[9]  Enrico Macii,et al.  NBTI-aware sleep transistor design for reliable power-gating , 2009, GLSVLSI '09.

[10]  Kaustav Banerjee,et al.  Aging-resilient design of pipelined architectures using novel detection and correction circuits , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[11]  V. Reddy,et al.  A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[12]  Chingwei Yeh,et al.  Timing driven power gating , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[14]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Kewal K. Saluja,et al.  Combating NBTI Degradation via Gate Sizing , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[16]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[17]  Shih-Chieh Chang,et al.  An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[18]  Robert P. Dick,et al.  Minimization of NBTI performance degradation using internal node control , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[20]  Diana Marculescu,et al.  Joint logic restructuring and pin reordering against NBTI-induced performance degradation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[21]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.