A 0.168/spl mu/m/sup 2//0.11/spl mu/m/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

A high performance embedded DRAM cell has been developed in 90nm technology using a pass transistor with standard 2.2nm gate oxide and trench capacitor. This device offers 25% on-current improvement with 1.5V wordline boosted voltage, and reduces the cell size by 10%. Measured data retention of >200/spl mu/s is ideal for 200+MHz random access cycle embedded DRAM macro with a concurrent refresh mode. The scalability of the cell to 0.11 /spl mu/m/sup 2/ in 65-nm node is also demonstrated.