ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite: Special session paper: CAD contest

Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular applications. From practical experience, the run time yielded by solving SAT problems using the default setting is far from best run time; same is true for CNF encoding. In this contest, we ask the participants to design the algorithm for exploring the best setting based on some sample cases, and we determine the contest winners by evaluating the run time for solving the remaining problems. The benchmark suites are extracted from the real designs in our applications of interest. We look forward to triggering the academic area in further investigating this problem.

[1]  Jinbo Huang,et al.  The Effect of Restarts on the Efficiency of Clause Learning , 2007, IJCAI.

[2]  Robert K. Brayton,et al.  SAT-based complete don't-care computation for network optimization , 2005, Design, Automation and Test in Europe.

[3]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[4]  Armin Biere.  Lingeling, Plingeling and Treengeling Entering the SAT Competition 2013 , 2013 .

[5]  Armin Biere,et al.  Clause Elimination Procedures for CNF Formulas , 2010, LPAR.

[6]  Miroslav N. Velev,et al.  Efficient translation of Boolean formulas to CNF in formal verification of microprocessors , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[7]  Alan Mishchenko,et al.  Applying Logic Synthesis for Speeding Up SAT , 2007, SAT.

[8]  Chung-Yang Huang,et al.  A false-path aware Formal Static Timing Analyzer considering simultaneous input transitions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[9]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[10]  Armin Biere,et al.  Effective Preprocessing in SAT Through Variable and Clause Elimination , 2005, SAT.

[11]  Aaron R. Bradley,et al.  SAT-Based Model Checking without Unrolling , 2011, VMCAI.

[12]  R. Brayton,et al.  Improvements to Combinational Equivalence Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[13]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[14]  Panagiotis Manolios,et al.  Faster SAT solving with better CNF generation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Gilles Audemard,et al.  Predicting Learnt Clauses Quality in Modern SAT Solvers , 2009, IJCAI.