ATM Switch Architectures with Input-Output-Buffering: Effect of Input Traffic Correlation, Contention Resolution Policies, Buffer Allocation Strategies and Delay in Backpressure Signal

Abstract This paper investigates the robustness of nonblocking ATM switch architectures with input-output-buffering and backpressure control under correlated input traffic conditions. Traffic correlation is modeled by two parameters: the mean active duration of the ON-OFF source feeding each input port and the spacing between the cells generated within an active period. This spacing can be fixed or random. The effect of these parameters on the switch performance in terms of the maximum switch throughput, and the cell loss behavior is investigated. The gain in throughput provided by the input-output-buffered architecture and the backpressure control mechanism over the pure input buffered architecture is investigated for different switch sizes and mean burst lengths. Detailed algorithmic descriptions and a possible implementation approach of the different selection mechanisms needed to resolve output port contention are presented. The performance of these selection mechanisms is evaluated, taking into consideration the performance enhancements provided by incorporating different arbitration criteria within the selection mechanisms. The critical issue of allocating the available buffer memory between the input and output ports for a fixed buffer budget is examined. The effect of traffic correlation on the buffer allocation strategies is also presented. The problems caused by the delay in the backpressure signal arising in possible implementations, particularly in a centralized control approach, are presented and analyzed in detail.

[1]  Michel Servel,et al.  The 'Prelude' ATD experiment: assessments and future prospects , 1988, IEEE J. Sel. Areas Commun..

[2]  David M. Lucantoni,et al.  Buffer sizing for synchronous self‐routeing broadband packet switches with bursty traffic , 1989 .

[3]  A. Descloux.  CONTENTION PROBABILITIES IN PACKET SWITCHING NETWORKS WITH STRUNG INPUT PROCESSES , 1988 .

[4]  Soung Chang Liew,et al.  Comparison of Buffering Strategies for Asymmetric Packet Switch Modules , 1991, IEEE J. Sel. Areas Commun..

[5]  San-Qi Li,et al.  Performance of a nonblocking space-division packet switch with correlated input traffic , 1992, IEEE Trans. Commun..

[6]  Anthony S. Acampora,et al.  The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..

[7]  Fouad A. Tobagi,et al.  Fast packet switch architectures for broadband integrated services digital networks , 1990, Proc. IEEE.

[8]  Masayuki Murata,et al.  Effect of speedup in nonblocking packet switch , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[9]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[10]  Achille Pattavina,et al.  Performance evaluation of an input-queued ATM switch with internal speed-up and finite output queues , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[11]  S. C. Liew.  Performance of input-buffered and output-buffered ATM switches under bursty traffic: simulation study , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[12]  S.-Q. Li.  Performance of a non-blocking space-division packet switch with correlated input traffic , 1989, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond.

[13]  J.W. Roberts,et al.  Variable-bit-rate traffic control in B-ISDN , 1991, IEEE Communications Magazine.

[14]  Thomas E. Stern,et al.  Throughput Analysis, Optimal Buffer Allocation, and Traffic Imbalance Study of a Generic Nonblocking Packet Switch , 1991, IEEE J. Sel. Areas Commun..

[15]  Joseph Y. Hui,et al.  A Broadband Packet Switch for Integrated Transport , 1987, IEEE J. Sel. Areas Commun..

[16]  Thomas G. Robertazzi.  Stochastic Models for ATM Switching Networks , 1993 .

[17]  M. J. Karol,et al.  Queueing in space-division packet switching , 1988, IEEE INFOCOM '88,Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?.

[18]  Hamid Ahmadi,et al.  A high-performance switch fabric for integrated circuit and packet switching , 1988, IEEE INFOCOM '88,Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?.

[19]  Wolfgang E. Denzel,et al.  Performance of packet switches with input and output queueing , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[20]  Satoshi Nojima,et al.  Integrated Services Packet Network Using Bus Matrix Switch , 1987, IEEE J. Sel. Areas Commun..

[21]  Achille Pattavina,et al.  Performance Evaluation of a Batcher-Banyan Interconnection Network with Output Pooling , 1991, IEEE J. Sel. Areas Commun..

[22]  Hussein T. Mouftah,et al.  Head of line arbitration in ATM switches with input-output buffering and backpressure control , 1991, IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record.

[23]  Hamid Ahmadi,et al.  A survey of modern high-performance switching techniques , 1989, IEEE J. Sel. Areas Commun..

[24]  Hussein T. Mouftah,et al.  Fairness for broadband integrated switch architectures under backpressure mechanisms , 1991, ICC 91 International Conference on Communications Conference Record.