DC-link loop bandwidth selection strategy for grid-connected inverters considering power quality requirements

Abstract DC-link voltage and output current control loops are two cascaded loops in the control structure of grid-connected inverters. A high DC-link voltage loop bandwidth (DCL-BW) provides more disturbance rejection capability for the control loop and is preferred from control system perspective. However, for stability issues, this BW is limited and must be sufficiently less than that of the current control loop. Among the different control schemes, instantaneous active reactive control (IARC) method provides the highest possible DCL-BW (i.e., 0.02 × switching frequency). Having this degree of freedom in the controller design, a proper methodology should be defined for selection of DCL-BW. In this paper, different factors including the output current harmonic distortion, low-order harmonics on DC link voltage, and the inverter nominal rating are introduced as affecting parameters for DCL-BW selection. Accordingly, a DCL-BW selection strategy based on output current harmonic distortion is proposed. The proposed method enhances the power quality indices of the grid-connected inverters, which especially is useful for few kVA power inverters. Finally, to validate the conducted analysis, experimental and simulation results are provided.