High-throughput layered decoder implementation for quasi-cyclic LDPC codes

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.

[1]  Yanni Chen,et al.  A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[2]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Rüdiger L. Urbanke,et al.  Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[4]  Luca Fanucci,et al.  Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

[5]  Daniel A. Spielman,et al.  Improved low-density parity-check codes using irregular graphs and belief propagation , 1998, Proceedings. 1998 IEEE International Symposium on Information Theory (Cat. No.98CH36252).

[6]  Yeong-Luh Ueng,et al.  VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[7]  Shu Lin,et al.  Two simple stopping criteria for turbo decoding , 1999, IEEE Trans. Commun..

[8]  Jean-Luc Danger,et al.  Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes , 2003 .

[9]  Tong Zhang,et al.  On finite precision implementation of low density parity check codes decoder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[10]  Marc P. C. Fossorier,et al.  Shuffled iterative decoding , 2005, IEEE Transactions on Communications.

[11]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[12]  Naresh R. Shanbhag,et al.  High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Simon Litsyn,et al.  Efficient Serial Message-Passing Schedules for LDPC Decoding , 2007, IEEE Transactions on Information Theory.

[14]  Payam Pakzad,et al.  VLSI architectures for iterative decoders in magnetic recording channels , 2001 .

[15]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[16]  Shyh-Jye Jou,et al.  An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications , 2008, IEEE Journal of Solid-State Circuits.

[17]  Radford M. Neal,et al.  Near Shannon limit performance of low density parity check codes , 1996 .

[18]  Frank Kienle,et al.  A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.

[19]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[20]  Joseph R. Cavallaro,et al.  Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[21]  Daniel A. Spielman,et al.  Efficient erasure correcting codes , 2001, IEEE Trans. Inf. Theory.

[22]  D.E. Hocevar,et al.  A reduced complexity decoder architecture via layered decoding of LDPC codes , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[23]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[24]  Zhongfeng Wang,et al.  Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Xin-Yu Shih,et al.  An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$m CMOS Process , 2008, IEEE Journal of Solid-State Circuits.

[26]  In-Cheol Park,et al.  Loosely coupled memory-based decoding architecture for low density parity check codes , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[28]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[29]  Keshab K. Parhi,et al.  VLSI implementation-oriented (3, k)-regular low-density parity-check codes , 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

[30]  Mohammed Atiquzzaman,et al.  VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax , 2007, 2007 IEEE International Conference on Communications.

[31]  Manabu Hagiwara,et al.  Quasicyclic low-density parity-check codes from circulant permutation matrices , 2009, IEEE Transactions on Information Theory.