A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-¿m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ¿m2.

[1]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[2]  Kari Halonen,et al.  1-V 9-bit pipelined switched-opamp ADC , 2001 .

[3]  F. Kuttner.  A 1.2V 10b 20MS/S Non-Binary Successive Approximation ADC in 0.13μm CMOS , 2002 .

[4]  D. Draxelmayr,et al.  A 6b 600MHz 10mW ADC array in digital 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[5]  R.W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS , 2006, IEEE Journal of Solid-State Circuits.

[6]  Robert W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .

[7]  Sanroku Tsukamoto,et al.  A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  Chorng-Kuang Wang,et al.  A 8-bit 500-KS/s low power SAR ADC for bio-medical applications , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[9]  M. Vertregt,et al.  A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[10]  B.P. Ginsburg,et al.  500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , 2007, IEEE Journal of Solid-State Circuits.

[11]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[12]  Brian P. Ginsburg,et al.  Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[13]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification , 2008, 2008 IEEE Symposium on VLSI Circuits.

[14]  Eric Andre,et al.  A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[15]  Kiat Seng Yeo,et al.  An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Andrea Baschirotto,et al.  An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[17]  Bram Nauta,et al.  A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[18]  B.P. Ginsburg,et al.  Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[19]  Shouli Yan,et al.  A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[20]  L. Richard Carley,et al.  ADC in 45nm LP Digital CMOS , 2009 .

[21]  Soon-Jyh Chang,et al.  A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process , 2009, 2009 Symposium on VLSI Circuits.

[22]  Gin-Kou Ma,et al.  A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.