A new column redundancy scheme for fast access time of 64-Mb DRAM

A 3.3-V 64-Mbit DRAM is fabricated using 0.4-/spl mu/m CMOS triple poly and double metal process technology. The DRAM implements a new column redundancy scheme called the data line suppression (DLS) to achieve fast access time. The widely used redundancy method for DRAMs (the address suppression scheme) has the disadvantage that access time for the redundancy column is longer than the normal column. The new DLS scheme overcomes this problem. A full chip 64-Mb DRAM which incorporates the new redundancy scheme is designed and successfully fabricated. Measurements confirm that column access time (t/sub AA/) for both the normal and redundant column are identical. It is 27 ns for typical operating conditions.<<ETX>>

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