Optimized Design and Simulation Based on FPGA of IC Card

Considering the problem of the chip area and the speed during the design of digital circuit,this paper put forward an optimization method of the AES algorithm.In this paper,the operation of encryption and decryption used the same memorizer.Aiming at the encryption which grouped for 128 bit,we also gave an optimization methods of its structure,in which the extension of the key and the blocker of the encryption and decryption used the same four changing boxes,thus fully using the hardware resource.In this way,we attained a high ratio of the speed to the area.Based on this method,we designed a AES processor which could meet the demand of IC card.Later,the design was simulated on the operation flat of the XilinixISE6.0,which was impoldered by the corporation of Xilinx.From the simulation result,we could see that the speed of encryption and decryption satisfied the requirement of IC card for the AES processor,which showed that the design was feasible.