FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis

Digital signal processing (DSP) based applications are designed using various types of DSP algorithms which are computationally intensive. So, DSP-based applications widely utilize Multiply-Accumulate (MA C) operation for accomplishing speed. In contrast with the binary number system, Residue Number Systems (RNS) is considered to be more prominent because of their abilities of carrying out carry-free arithmetic operations like addition, subtraction. Ternary value logic (TVL) offers several advantages like reduced chip area as well as overall delay, over conventional binary number system. Designing superior adder and multiplier have become the major concern for implementing high performance signal processing applications. To improve the performance of MA C unit, a new architecture is proposed in this paper. In this paper, MA C unit is implemented using ternary multiplier and RNS adder in TVL domain. The major bottleneck of TVL to RNS conversion and vice versa has introduced huge complexity which leads to decreased efficiency of performance due to large conversion time. The performance of RNS based system can be enhanced by choosing relative prime moduli set as improper selection of moduli will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.

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