FPGA-based combined architecture for stream categorization and intrusion detection

This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The solution implements pattern matching logic for all the mandatory and optional patterns while maintaining the required line rate of 500 Mbps.

[1]  Shan Shan Huang,et al.  Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary , 2008, ECOOP.

[2]  Sung-Mo Kang,et al.  An empirical model for accurate estimation of routing delay in FPGAs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  Forrest Brewer,et al.  Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID) , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[4]  Joshua S. Auerbach,et al.  Lime: a Java-compatible and synthesizable language for heterogeneous architectures , 2010, OOPSLA.