Organization of the Motorola 88110 superscalar RISC microprocessor

Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described.<<ETX>>

[1]  G. Amdhal,et al.  Validity of the single processor approach to achieving large scale computing capabilities , 1967, AFIPS '67 (Spring).

[2]  Gordon Bell,et al.  An Investigation of Alternative Cache Organizations , 1974, IEEE Transactions on Computers.

[3]  M.J. Phillip.  Performance issues for the 88110 RISC microprocessor , 1992, Digest of Papers COMPCON Spring 1992.

[4]  Carlo H. Séquin,et al.  A VLSI RISC , 1982, Computer.

[5]  Randy H. Katz,et al.  Implementing a cache consistency protocol , 1985, ISCA 1985.

[6]  Tom Kilburn,et al.  One-Level Storage System , 1962, IRE Trans. Electron. Comput..

[7]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[8]  R. M. Tomasulo,et al.  An efficient algorithm for exploiting multiple arithmetic units , 1995 .

[9]  George Radin,et al.  The 801 minicomputer , 1982, ASPLOS I.

[10]  Norman P. Jouppi,et al.  Available instruction-level parallelism for superscalar and superpipelined machines , 1989, ASPLOS 1989.

[11]  Henry G. Dietz,et al.  Improving cache performance by selective cache bypass , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

[12]  Andrew R. Pleszkun,et al.  Implementing Precise Interrupts in Pipelined Processors , 1988, IEEE Trans. Computers.

[13]  Michel Dubois,et al.  Synchronization, coherence, and event ordering in multiprocessors , 1988, Computer.

[14]  Shlomo Weiss,et al.  Instruction issue logic for pipelined supercomputers , 1984, ISCA 1984.

[15]  D. J. Lalja,et al.  Reducing the branch penalty in pipelined processors , 1988, Computer.

[16]  Jacob A. Abraham,et al.  Using write back cache to improve performance of multi-user multiprocessors , 1982, ICPP.

[17]  James E. Smith,et al.  Dynamic instruction scheduling and the Astronautics ZS-1 , 1989, Computer.

[18]  W. H. Wang,et al.  Organization and performance of a two-level virtual-real cache hierarchy , 1989, ISCA '89.