Capacity Loss Factors in Semiconductor Manufacturing

This paper describes characteristics and problems of the capacity planning process in semiconductor wafer fabrication facilities. Twenty-two factors that contribute to capacity loss are identified and discussed. Informaton on these loss factors was obtained through three sources: 1) a literature review; 2) an extensive survey, interview, and workshop process; and 3) a variety of queueing and simulation models.

[1]  Y. Narahari,et al.  Modeling re-entrant manufacturing systems with inspections , 1995, Proceedings of 1995 IEEE International Conference on Robotics and Automation.

[2]  S. J. Hood Detail vs. simplifying assumptions for simulating semiconductor manufacturing lines , 1990, Ninth IEEE/CHMT International Symposium on Electronic Manufacturing Technology,Competitive Manufacturing for the Next Decade.

[3]  David D. Yao,et al.  A queueing network model for semiconductor manufacturing , 1996 .

[4]  S.C.H. Lu,et al.  Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants , 1994 .

[5]  K. Kempf,et al.  Simulation of emergent behavior in manufacturing systems , 1995, Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop.

[6]  David Y. Burman,et al.  Performance analysis techniques for IC manufacturing lines , 1986, AT&T Technical Journal.

[7]  John W. Fowler,et al.  Measurement and improvement of manufacturing capacity (mimac) designed experiment report , 1995 .

[8]  S. S. Panwalkar,et al.  A Survey of Scheduling Rules , 1977, Oper. Res..

[9]  Christopher S. Tang Designing an optimal production system with inspection , 1991 .

[10]  G. Leonovich An approach for optimizing WIP/cycle time/output in a semiconductor fabricator , 1994, Proceedings of 16th IEEE/CPMT International Electronic Manufacturing Technology Symposium.

[11]  P. Tran-Gia,et al.  Discrete-Time Analysis of Batch Servers with Bounded Idle Time , 1996, ESM.

[12]  Gregory Dobson,et al.  The Batch Loading and Scheduling Problem , 2001, Oper. Res..

[13]  Jonathan F. Bard,et al.  The use of upstream and downstream information in scheduling semiconductor batch operations , 1995 .

[14]  W. J. Trybula "Hot" jobs, bane or boon , 1993, Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium.

[15]  Lawrence M. Wein,et al.  Scheduling semiconductor wafer fabrication , 1988 .

[16]  Gabriel R. Bitran,et al.  Tradeoff Curves, Targeting and Balancing in Manufacturing Queueing Networks , 1989, Oper. Res..

[17]  Asbjoern M. Bonvik Estimating the Lead Time Distribution of Priority Lots in a Semiconductor Factory , 1994 .

[18]  D.S. O'Ferrell,et al.  Manufacturing modeling and optimization , 1995, Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop.

[19]  C. Moorehead All rights reserved , 1997 .

[20]  Pius J. Egbelu,et al.  Scheduling in a manufacturing shop with sequence-dependent setups , 1989 .

[21]  Vincent A. Mabert,et al.  AN EVALUATION OF ORDER RELEASE MECHANISMS IN A JOB-SHOP ENVIRONMENT , 1988 .

[22]  P. O'Neil Performance evaluation of lot dispatching and scheduling algorithms through discrete event simulation , 1991, 1991 Proceedings IEEE/SEMI International Semiconductor Manufacturing Science Symposium.

[23]  Uday S. Karmarkar,et al.  Capacity analysis of a manufacturing cell , 1987 .

[24]  David J. Miller,et al.  Simulation of a semiconductor manufacturing line , 1990, CACM.

[25]  Stanley B. Gershwin,et al.  Scheduling manufacturing systems with work-in-process inventory control: Reentrant systems , 1991 .

[26]  W. Whitt,et al.  The Queueing Network Analyzer , 1983, The Bell System Technical Journal.

[27]  Y. Narahari,et al.  Performance analysis of scheduling policies in re-entrant manufacturing systems , 1996, Comput. Oper. Res..

[28]  Lawrence M. Wein,et al.  On the relationship between yield and cycle time in semiconductor wafer fabrication , 1992 .

[29]  Pravin K. Johri,et al.  Practical issues in scheduling and dispatching in semiconductor wafer fabrication , 1993 .

[30]  Susan S. Baum,et al.  An approach to modeling labor and machine down time in semiconductor fabrication , 1991, 1991 Winter Simulation Conference Proceedings..

[31]  Pravin K. Johri Overlapping machine groups in semiconductor wafer fabrication , 1994 .

[32]  A. Spence,et al.  Capacity planning of a photolithography work cell in a wafer manufacturing line , 1987, Proceedings. 1987 IEEE International Conference on Robotics and Automation.

[33]  R. C. Leachman,et al.  An improved methodology for real-time production decisions at batch-process work stations , 1993 .

[34]  Jon Lee,et al.  Order selection on a single machine with high set-up costs , 1993, Ann. Oper. Res..

[35]  Mauricio G. C. Resende,et al.  Closed-loop job release control for VLSI circuit manufacturing , 1988 .

[36]  A. G. Lockett,et al.  Using Simulation in Capacity Planning , 1991 .

[37]  D. P. Martin Key factors in designing a manufacturing line to maximize tool utilization and minimize turnaround time , 1993, [1993 Proceedings] IEEE/SEMI International Semiconductor Manufacturing Science Symposium.

[38]  Timothy D. Fry,et al.  Capacity-based order review/release strategies to improve manufacturing performance , 1992 .

[39]  C. R. Glassey,et al.  Dynamic batching heuristic for simultaneous processing , 1991 .

[40]  P. R. Kumar,et al.  Re-entrant lines , 1993, Queueing Syst. Theory Appl..

[41]  Don T. Phillips,et al.  A comparison of order release strategies in production control systems , 1992 .

[42]  Debasis Mitra,et al.  Analysis of a Kanban discipline for cell coordination in production lines , 1990 .

[43]  Judith E. Dayhoff,et al.  Signature analysis of dispatch schemes in wafer fabrication , 1986 .

[44]  John W. Fowler,et al.  Measurement and improvement of manufacturing capacities (MIMAC): Final report , 1995 .

[45]  Uday S. Karmarkar,et al.  Lot Sizes, Lead Times and In-Process Inventories , 1987 .

[46]  Don T. Phillips,et al.  A state-of-the-art survey of dispatching rules for manufacturing job shop operations , 1982 .

[47]  Robert C. Leachman,et al.  On Capacity Modeling for Production Planning with Alternative Machine Types , 1992 .

[48]  D. Rohan Resource sharing in capacity analysis , 1992, IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - ASMC '92 Proceedings.

[49]  John W. Fowler,et al.  Real-time control of multiproduct bulk-service semiconductor manufacturing processes , 1992 .

[50]  Averill M. Law Models of random machine downtimes for simulation , 1990, 1990 Winter Simulation Conference Proceedings.

[51]  Najmi Adeel Management of cycle time in semiconductor wafer fabrication , 1993 .

[52]  N. Abt,et al.  Cost Analysis for a Multiple Product / Multiple Process Factory: Application of SEMATECH's Future Factory Design Methodology , 1993, Proceedings. IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop.

[53]  U. Karmarkar,et al.  Manufacturing configuration, capacity and mix decisions considering operational costs , 1987 .

[54]  Hau L. Lee,et al.  Production Control in Multistage Systems with Variable Yield Losses , 1988, Oper. Res..

[55]  R. G. Petrakian,et al.  Trade-offs in cycle time management: hot lots , 1992 .

[56]  Wallace J. Hopp,et al.  Throughput of a constant work in process manufacturing line subject to failures , 1991 .

[57]  Ram Akella,et al.  Control of batch processing systems in semiconductor wafer fabrication facilities , 1992 .

[58]  Lee J. Krajewski,et al.  Kanban, MRP, and Shaping the Manufacturing Environment , 1987 .

[59]  J. A. Cunningham The use and evaluation of yield models in integrated circuit manufacturing , 1990 .

[60]  Wallace J. Hopp,et al.  Machine Maintenance with Multiple Maintenance Actions , 1990 .

[61]  Vijay Mehrotra,et al.  From spreadsheets to simulations: a comparison of analysis methods for IC manufacturing performance , 1992, [1992 Proceedings] IEEE/SEMI International Semiconductor Manufacturing Science Symposium.