An adequate measurement metrology to nondestructively verify the integrity of dielectric gap-fill in a deep trench (DT) capacitor of deep-submicron DRAM product was proposed. Because of the geometric structure in the DT capacitor, the vertical cylindrical electrode isolator approximately provides a parasitic NMOSFET. Through the electrical measurement, people can analyze these drain-to-source electrical characteristics. Some of most valuable device parameters, threshold voltage (Vt) and mobility (un), correlate to the interface integrity and the surface roughness between silicon substrate and gap-fill oxide (or liner oxide). In other words, as these values are obtained, the degradation level of this interface or gap-fill quality can be clarified. Indirectly, the charge storage quality of this capacitor, avoiding the leakage path, is able to be improved with the process modification.
[1]
Costas J. Spanos,et al.
Introduction to Semiconductor Manufacturing
,
2006
.
[2]
G. Groeseneken,et al.
Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation
,
1989
.
[3]
A. Tasch,et al.
Models for electron and hole mobilities in MOS accumulation layers
,
1999
.
[4]
Fabio Pellizzer,et al.
A new model of gate capacitance as a simple tool to extract MOS parameters
,
2001
.
[5]
J R A Beale,et al.
Solid State Electronic Devices
,
1973
.
[6]
Hong Xiao,et al.
Introduction to Semiconductor Manufacturing Technology
,
2000
.