A 5.5-GHz 3mW LNA and inductive degenerative CMOS LNA noise figure calculation

This paper, presents a precise noise figure formula for inductive degeneration CMOS LNAs. Also a fully integrated CMOS LNA with on-chip spiral inductors in 0.18 ¿m CMOS technology for 5.5-GHz unlicensed national information infrastructure (U-NII), 802.11a and IEEE 802.11n wireless LAN receivers is presented in this paper. Using a cascode current reuse structure with inter-stage inductors we achieved low power consumption and high power gain. We proved that the interstage inductors must be designed with a new method compared to newly published papers. This structure is based on two cascode configuration which provides a good output swing thus allowing the integration in low voltage technology. This configuration also permits good input impedance matching, low noise figure and high reverse isolation. Complete simulations of the circuit at 5.5-GHz center frequency, have shown that the circuit has 3.1 dB NF, 1.2 GHz 3 dB power bandwidth, 20.63 dB power gain (S21), high reverse isolation (S12)<-45 dB, -29.4 dB input matching (S11), -25 dB output matching (S22), and -15.9 dBm 3rd order input intercept point (IIP3). The power consumption is 3 mW at 1.8 V supply voltage.

[1]  Huey-Ru Chuang,et al.  A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver , 2003 .

[2]  M.J. Deen,et al.  A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching , 2006, IEEE Microwave and Wireless Components Letters.

[3]  Ali Telli,et al.  CMOS LNA design for LEO space S-band applications , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[4]  R. Havens,et al.  Noise modeling for RF CMOS circuit simulation , 2003 .

[5]  D. K. Shaeffer,et al.  Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier" , 2005, IEEE J. Solid State Circuits.

[6]  Sang-Gug Lee,et al.  A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance , 2003, IEEE J. Solid State Circuits.

[7]  Leonid Belostotski,et al.  Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Jeng-Han Tsai,et al.  A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology , 2006 .

[9]  Yuhua Cheng,et al.  High-frequency small signal AC and noise modeling of MOSFETs for RF IC design , 2002 .

[10]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[11]  T. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996 .

[12]  Yeo Kiat Seng,et al.  A modified architecture used for input matching in CMOS low-noise amplifiers , 2005 .

[13]  Eric Hanssen,et al.  Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[14]  Jeng-Han Tsai,et al.  A Miniature Q-Band Low Noise Amplifier Using 0.13- m CMOS Technology , 2009 .

[15]  P. R. Mukund,et al.  A tuned wideband LNA in 0.25 /spl mu/m IBM process for RF communication applications , 2004, 17th International Conference on VLSI Design. Proceedings..

[16]  Sungkyung Park,et al.  Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology , 2001, IEEE Trans. Consumer Electron..

[17]  G. Roientan Lahiji,et al.  A low-power and high-gain fully integrated CMOS LNA , 2007, Microelectron. J..