Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier

Various kinds of cryptosystems with advanced functions, such as ID-based and attribute-based cryptography, are expected as the solution for problems in the IoT era. Pairing computation is considered to be one of the promising components to construct such advanced cryptosystems. However, the computation time of the pairing, which involves the processing of complicated algebraic calculations, is a major obstacle for achieving the practical application. Previous studies in hardware implementation pairings mainly aim to improve the performance of the area-time product. While these studies prefer the usage of the resource-restricted environment, some server-side applications, such as attribute-based encryption for video streaming, require the implementation of low latency instead of the area-time product. This study proposes a low-latency pairing processor architecture and its optimal pipeline scheduling. The proposed architecture is implemented on Xilinx Virtex-6 ML605 and Virtex Ultrascale+ VCU118 board, and we confirmed that these implementations complete single pairing computation within 153 μs and 61 μs, respectively.