论文信息 - Part I: Conclusions and Future Directions

Part I: Conclusions and Future Directions

Chapter 2 described some existing leakage reduction techniques. Threemain classes of techniques were discussed – power gating, body biasing and input vector control. Each of these techniques have their pros and cons and there is no one “one-size-fitsall” technique that solves the leakage problem for all designs.

Sunil P. Khatri | Rajesh Garg | Suganth Paul | Kanupriya Gulati | Nikhil Jayakumar

[1] Mark C. Johnson,et al. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[2] R. Rao,et al. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits , 2003, ICCAD 2003.

[3] Enrico Macii,et al. Algebric Decision Diagrams and Their Applications , 1997, ICCAD '93.

[4] Mark C. Johnson,et al. Models and algorithms for bounds on leakage in CMOS circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5] David Blaauw,et al. Robust SAT-Based Search Algorithm for Leakage Power Reduction , 2002, PATMOS.

[6] Feng Gao,et al. Exact and heuristic approaches to input vector control for leakage power reduction , 2004, ICCAD 2004.

[7] A.P. Chandrakasan,et al. Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[8] Farid N. Najm,et al. A gate-level leakage power reduction method for ultra-low-power CMOS circuits , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.