Design automation of digital circuits for partially depleted SOI-technology

This paper shows that it is possible to adapt commercially available layout generators to the specific needs of partially depleted (PD)-SOI-technologies with minimal area penalty. Therefore, the requirements of SOI-specific layout techniques are investigated. A design flow for automatic layout generation is proposed. An implementation is presented with a cell library created with this generator. Measurements of test circuitry at temperatures up to 390 /spl deg/C and supply voltages up to 10 V are shown.