Chip failpoint positioning method

The invention provides a chip failpoint positioning method, and relates to the semiconductor technical field; the chip failpoint positioning method comprises the following steps: S101, providing a failpoint chip comprising a device and a metal layer positioned above the device; S102, removing a portion, beside which a probe contact is to be conducted, of the metal layer so as to form a metal contact point; S103, employing the probe to contact with the metal contact point so as to carry out failpoint positioning; the chip failpoint positioning method keeps the metal layer on a position, in which the probe contact is to be conducted, of the chip so as to form the metal contact point, so the probe cannot directly contact with a device surface of the chip, thereby preventing damage to the device by the probe, and improving success rate and accuracy of the chip failpoint positioning.