The Viterbi algorithm is a fundamental signal-processing technique used in different communication systems. An improved, implemented, and tested approximate squaring function for the Viterbi algorithm is introduced in this paper. The implementation of this improved squaring function is based on combinational logic design. The performance of this new approach has been verified by implementing a 7-bit squaring function chip in a 2-/spl mu/m CMOS technology. The active integrated circuit area of the chip was 380/spl times/400 /spl mu/m/sup 2/, and the delays through this area were 5.7 and 3.0 ns for rising and falling edges, respectively. Compared with a previous design, this approach reduces error associated with approximation, simplifies the complexity of realization, reduces the integrated circuit area by at least 40%, and increases the speed by about 100%.
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