Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Self-heating can lead to excessive temperatures in large power DMOS transistors, thus restricting their safe oper- ating area (SOA). To explore that limit, the device temperature must be known with sufficient accuracy, which is difficult in advanced BCD technologies. This is because standard measure- ment methods such as infrared thermography do not show the true device temperature. Also, most (electro-)thermal simulation approaches have not been experimentally verified close to the SOA limits. In this work, a test chip with novel temperature sensors embedded inside the DMOS cell array will be used for accurate measurements of the device temperature. Moreover, a 3-D numer- ical temperature simulator is extended to correctly consider the temperature-dependent DMOS behavior. Thus, electro-thermal coupling is taken into account while simultaneously calculating the temperatures with high spatial resolution. The validity of the simulator will be demonstrated experimen- tally by comparison to measurements for temperatures exceeding 500 ◦ C, up to the onset of thermal runaway.

[1]  A. Irace,et al.  TherMos3: a 3D electrothermal simulator for Smart Power Devices , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[2]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[3]  B.H. Krabbenborg,et al.  Robustness of LDMOS power transistors in SOI-BCD processes and derivation of design rules using thermal simulation , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[4]  V. Parthasarathy,et al.  Detection and optimization of temperature distribution across large-area power MOSFETs to improve energy capability , 2004, IEEE Transactions on Electron Devices.

[5]  M. Stecher,et al.  Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[6]  R. Lachner,et al.  Simulation of self-heating in advanced high-speed SiGe bipolar circuits using the temperature simulator TESI , 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

[7]  V. d'Alessandro,et al.  Modeling the onset of thermal instability in low voltage power MOS: an experimental validation , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[8]  G. Wachutka,et al.  A modular high temperature measurement set-up for semiconductor device characterization , 2007, 2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC).

[9]  Giovanni Breglio,et al.  Thermal mapping and 3D numerical simulation of new cellular power MOS affected by electro-thermal instability , 2000 .

[10]  A. Consoli,et al.  Thermal instability of low voltage power-MOSFETs , 1999, 30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321).

[11]  V. d'Alessandro,et al.  Analytical model for thermal instability of low voltage power MOS and SOA in pulse operation , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[12]  Antonio Testa,et al.  Thermal instability of low voltage power-MOSFETs , 2000 .

[13]  M. Stecher,et al.  Influence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[14]  P. Dobson.  Physics of Semiconductor Devices (2nd edn) , 1982 .