An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain

This paper introduces an improved adaptive analog equalizer that is required in high speed serial receivers using four-level pulse amplitude modulation signaling. By performing boosting-state detection in the time domain, the proposed adaptive analog equalizer can effectively overcome a serious problem that the received signal’s eye-opening tends to be compromised by the convergence accuracy of the adaptive control loop. To suppress the pattern-dependent jitters (PDJs), an inductor-less, cross-stage feedback structure is employed in the proposed analog equalizer to help broaden its effective tuning bandwidth. Multichannel simulations have confirmed that the proposed equalizer is able to achieve a 42% improvement in eye-height opening when compared with the equalizers employing popular spectrum-comparing schemes. Trellis diagram analyses under different date rates have revealed that the bandwidth of the proposed equalizer can be extended by as much as 60%, thus effectively bringing the PDJs from 44% down to 27.5%.

[1]  W. Guggenbuhl,et al.  A versatile building block: the CMOS differential difference amplifier , 1987 .

[2]  Wolfgang Pribyl,et al.  Design Specification for BER Analysis Methods Using Built-In Jitter Measurements , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Takayuki Shibasaki,et al.  A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.

[4]  Jri Lee A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[5]  Peng Liu,et al.  A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver , 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

[6]  J. Caroselli,et al.  Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps) , 2007 .

[7]  Bo Zhang,et al.  3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[8]  Jri Lee,et al.  6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[9]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[10]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[11]  Qui-Ting Chen,et al.  A 4-PAM adaptive analog equalizer for backplane interconnections , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[12]  Takayuki Shibasaki,et al.  6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[13]  Chih-Fan Liao,et al.  A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery , 2008, IEEE Journal of Solid-State Circuits.

[14]  Matteo Bassi,et al.  A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  S.. Gondi,et al.  Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers , 2007, IEEE Journal of Solid-State Circuits.