Design and Implementation of a Low Power Successive Approximation ADC

This paper designed a low-power successive approximation ADC based on BCD 0.35um standard CMOS technology. The overall static power consumption of the circuit and the use of passive components has been reduced by using switch dynamic comparator and the comparator of the state transition controlled by the clock signal as well as the DAC circuit uses charge redistribution structure. The sample and hold circuit is built into the ADC which further reduce the size of the chip area. The parameters of DNL, INL, SINR and SINAD were verified by MATLAB software. At the same time HSPICE tools were used to simulate the successive approximation ADC. Under the condition of VCC = 3.3V, T = 25 ℃, the overall power consumption of the circuit is 1.518mW, and the SNR of the circuit is 50.93dB.