Low power CMOS full adder cells

This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and COUT.

[1]  Qin Wang,et al.  A new full adder design for tree structured arithmetic circuits , 2010, 2010 2nd International Conference on Computer Engineering and Technology.

[2]  Chip-Hong Chang,et al.  A novel hybrid pass logic with static CMOS output drive full-adder cell , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[4]  Yu-Cherng Hung,et al.  A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[5]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[6]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .