CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks

As feature size shrinks, routing constraints become a more significant limiting factor to the manufacturability of VLSI designs. Routing congestion significantly impacts quality metrics such as area and timing performance, but congestion is not known accurately until late in the design cycle, after placement and routing. This can lead to unpleasant surprises during the design process. Accordingly, early prediction of routing requirements would enable design engineers to iterate faster, with more confidence that their designs were routable and high quality. Additionally, routability estimates can inform placement itself, preemptively eliminating routing problems. In this work, we present a graph-based deep learning method for quickly predicting logic-induced routing congestion hotspots from a gate-level netlist before placement. This model can provide early feedback to designers and EDA tools, indicating logic that may be difficult to route. Compared to using previous congestion prediction metrics to predict congestion hotspots without placement information, our solution provides a 29% increase in the Kendall ranking correlation score. Because our focus is on predicting congestion due to local logic structure, which manifests itself on lower metal layers, we also report accuracy for predicting lower metal layer congestion. When predicting congestion for the lower metal layers, the benefit of our solution over previous metrics increases to 75%. Additionally, our approach is fast. On a circuit with 1.3 million cells, our approach takes 19 seconds to predict congestion, compared with 10–60 minutes for other methods.