Fixed cycle Huffman decoding instruction for multi-format decoder

A dedicated instruction for Huffman decoding being performed in a fixed cycle is proposed. To do this, Huffman table mapping algorithm is also proposed. It supports various types of Huffman code and optimum mapping table size can be set for the various configuration modes. Proposed instruction is applied to reconfigurable processor of VLIW/CGA architecture operating at up to 1GHz using 35nm CMOS technology and can decode a symbol in 5 cycles.

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