Detecting resistive-opens in RRAM using Programmable DfT scheme

Resistive Random Access Memory (RRAM) is one of the emerging memory devices that possesses a combined attribute of SRAM, DRAM and flash. However, as the technology and fabrication process of such a promising memory devices are still immature, RRAM is expected to be impacted by process-variation faults such as resistive-open. This kind of defect is difficult to be detected using existing Design-for-Testability (DfT) scheme, which is developed based on a single critical defect value. This paper presents a new DfT scheme with the capability to identify faulty RRAM cells impacted by resistive-opens due to process variation. The new DfT scheme, referred to as Programmable Low Write Voltage (PLWV), is based on multiple voltage levels that can be programmed to suit the target fault coverage. The concept, design methodology and circuit are described. SPICE simulation results suggest that the proposed PLWV scheme can detect faults with different defect values at minimal circuit modification.

[1]  Said Hamdioui,et al.  On Defect Oriented Testing for Hybrid CMOS/Memristor Memory , 2011, 2011 Asian Test Symposium.

[2]  Peng Li,et al.  Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Said Hamdioui,et al.  An experimental analysis of spot defects in SRAMs: realistic fault models and tests , 2000, Proceedings of the Ninth Asian Test Symposium.

[4]  L. Chua Memristor-The missing circuit element , 1971 .

[5]  S. Hamdioui,et al.  Why is CMOS scaling coming to an END? , 2008, 2008 3rd International Design and Test Workshop.

[6]  Ute Drechsler,et al.  Transition-metal-oxide-based resistance-change memories , 2008, IBM J. Res. Dev..

[7]  K. Eshraghian,et al.  The fourth element: characteristics, modelling and electromagnetic theory of the memristor , 2010, Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences.

[8]  A. M. Darsono,et al.  High-Performance, Fault-Tolerant Architecture for Reliable Hybrid Nanolectronic Memories , 2012 .

[9]  Said Hamdioui,et al.  DfT schemes for resistive open defects in RRAMs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Said Hamdioui,et al.  Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories , 2011, JETC.

[11]  J. Yang,et al.  Memristive switching mechanism for metal/oxide/metal nanodevices. , 2008, Nature nanotechnology.

[12]  Cong Xu,et al.  Design implications of memristor-based RRAM cross-point structures , 2011, 2011 Design, Automation & Test in Europe.

[13]  Said Hamdioui,et al.  Residue-based code for reliable hybrid memories , 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

[14]  D. Strukov,et al.  Prospects for terabit-scale nanoelectronic memories , 2004 .

[15]  Kailash Gopalakrishnan,et al.  Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..

[16]  D. Strukov,et al.  Defect-tolerant architectures for nanoelectronic crossbar memories. , 2007, Journal of nanoscience and nanotechnology.

[17]  C.M. Jeffery,et al.  Hierarchical fault tolerance for nanoscale memories , 2006, IEEE Transactions on Nanotechnology.

[18]  Tong Zhang,et al.  Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories , 2007, IEEE Transactions on Nanotechnology.