Energy-Efficient Phase-Aware Scheduling for Heterogeneous Multicore Processors

While the multicore processors common today are typically homogeneous (i.e. composed of multiple cores of identical design), ever-more-stringent energy and performance constraints are making heterogeneous multicore processors increasingly attractive alternatives. Because applications vary significantly in the computing resources that they can effectively exploit, they observe drastically different energy consumption and performance depending on the characteristics of the processor core(s) they are running on. Heterogeneous computing cores can more efficiently meet the specialized needs of varied applications. However, while heterogeneous types of cores can be beneficial, the added complexity of heterogeneity can significantly complicate the scheduling of application threads to cores of different types. To achieve energy efficiency, a scheduler must attempt to minimize energy consumption by finding the optimal application to core mapping. Most existing approaches to mapping applications to heterogenous cores do so statically-that is they determine a priori the fitness of a particular application thread to a particular core type. This paper demonstrates that significant reduction in energy consumption can be achieved by dynamically adjusting this mapping as application behavior changes with new program phases. This paper further proposes an online scheduler that re- evaluates the program-to-core assignment when a phase-change of a program occurs, in order to optimize the scheduler for energy consumption. Our results show significant energy reduction over random scheduling of programs within a heterogeneous multicore processor.

[1]  Dheeraj Reddy,et al.  Bias scheduling in heterogeneous multi-core architectures , 2010, EuroSys '10.

[2]  Brian N. Bershad,et al.  Execution characteristics of desktop applications on Windows NT , 1998, ISCA.

[3]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008 .

[4]  Flavius Gruian,et al.  System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors , 2000, PACS.

[5]  Norman P. Jouppi,et al.  Conjoined-Core Chip Multiprocessing , 2004, 37th International Symposium on Microarchitecture (MICRO-37'04).

[6]  Michael S. Hsiao,et al.  Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors , 2001, ISLPED '01.

[7]  Hridesh Rajan,et al.  Phase-based tuning for better utilization of performance-asymmetric multicore processors , 2011, International Symposium on Code Generation and Optimization (CGO 2011).

[8]  Lina Sawalha,et al.  Thread scheduling for heterogeneous multicore processors using phase identification , 2011, PERV.

[9]  Manuel Prieto,et al.  Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems , 2011, J. Parallel Distributed Comput..

[10]  Kay Chen Tan,et al.  A hybrid evolutionary approach for heterogeneous multiprocessor scheduling , 2009, Soft Comput..

[11]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[12]  Tajana Simunic,et al.  Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Stacey Jeffery,et al.  HASS: a scheduler for heterogeneous multicore systems , 2009, OPSR.

[14]  Gu-Yeon Wei,et al.  Thread motion: fine-grained power management for multi-core systems , 2009, ISCA '09.

[15]  Hyesoon Kim,et al.  Age based scheduling for asymmetric multiprocessors , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[16]  Lina Sawalha,et al.  Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors , 2011, 2011 14th Euromicro Conference on Digital System Design.

[17]  Margaret Martonosi,et al.  Long-term workload phases: duration predictions and applications to DVFS , 2005, IEEE Micro.

[18]  Manuel Prieto,et al.  A comprehensive scheduler for asymmetric multicore systems , 2010, EuroSys '10.

[19]  Joonwon Lee,et al.  Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors , 2008, IEEE Transactions on Parallel and Distributed Systems.

[20]  Lizy Kurian John,et al.  Energy-aware application scheduling on a heterogeneous multi-core system , 2008, 2008 IEEE International Symposium on Workload Characterization.

[21]  Cheng Wang,et al.  A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing , 2011, International Symposium on Code Generation and Optimization (CGO 2011).

[22]  Rami G. Melhem,et al.  Dynamic and aggressive scheduling techniques for power-aware real-time systems , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).

[23]  Rami G. Melhem,et al.  Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multiprocessor Real-Time Systems , 2003, IEEE Trans. Parallel Distributed Syst..

[24]  Patrick Crowley,et al.  Dynamic thread assignment on heterogeneous multiprocessor architectures , 2006, CF '06.

[25]  Grigori Fursin,et al.  Predictive Runtime Code Scheduling for Heterogeneous Architectures , 2008, HiPEAC.

[26]  Sanjay Ranka,et al.  Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems , 2011, Sustain. Comput. Informatics Syst..

[27]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[28]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[29]  Hong Jiang,et al.  Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[30]  Jun Shirako,et al.  Software-cooperative power-efficient heterogeneous multi-core for media processing , 2008, 2008 Asia and South Pacific Design Automation Conference.

[31]  Joonwon Lee,et al.  Optimal intratask dynamic voltage-scaling technique and its practical extensions , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..