CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with diameter down to ~ 20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. n- and p-MOS devices thus fabricated with gate length ~ 120 nm to 150 nm showed excellent transistor characteristics with large drive current per wire, high Ion/Ioff ratio (~ 107), good subthreshold slope (~ 80 mV/dec) and low DIBL (~ 20 mV/ V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

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