Trading Accuracy for Power in a Multiplier Architecture

Certain classes of applications are inherently capable of absorbing some error in computation, which allows for quality to be traded off for power. Such a tradeoff is often achieved through voltage over-scaling. We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 multiplier as its building block. Our inaccurate multipliers achieve an average power saving of 31.78%− 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%−3.32%. We compare our architecture with other approaches, such as voltage scaling, for introducing error in a multiplier. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X 8X better SignalNoise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design-dependent. We compare this circuit-centric approach to power-quality tradeoffs with a pure software adaptation approach for a JPEG example. Unlike recent design-for-error approaches for arithmetic logic, we also enhance the design to allow for correct operation of the multiplier using a correction unit, for non error-resilient applications which share the hardware resource.